Responsible for design verification of mixed signal IC’s in a digital / mixed signal design environment
Proficiency in System Verilog including writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups, etc.
Support customers during project reviews or status calls
Primary focus is on mixed signal design verification, but proficiency with digital design verification (including UVM) is an plus
Creation and validation of System Verilog models for mixed signal circuit blocks
Creation of test benches and automated verification simulations
Experience running both analog (SPICE) and digital simulators is a strong advantage
Performing block level and top level design verification
Generation of relevant documentation (DV Plan, DV execution plan, customer reviews etc.)
Experience on electrical checks, static and dynamic, is a plus.
Master’s or Bachelor’s degree in Electrical / Computer Engineering with 3 years of experience in Design Verification
System Verilog / UVM based mixed signal DV (Design Verification) experience
Collaborative and respectful team player and passionate about achieving team goals
Excellent communication skills (both oral and written) are required, as real time customer level technical interface and design / team leadership is necessary.
Experience with relevant CAD tools