This company in Romania has been leading the way in semiconductor development, taking chips from conception to market readiness since its establishment in 2005. As we aim to expand and enhance our expertise, an exciting opportunity has emerged for the establishment of a new team dedicated to memory applications. We are in search of a talented and passionate individual to step into a leadership role focused on Digital Design within our new team. This position will be instrumental in shaping the growth and success of the team, offering the opportunity to contribute expertise and drive forward our commitment to advancing the semiconductor industry.
Employer Profile
semiconductors
Responsibilities
As a Principal Engineer for RTL Synthesis and STA, you will bear full responsibility for RTL2GDS planning, effort estimation, and implementation, ensuring the quality of the flow aligns with required KPIs.
In your new role you will:
Lead the RTL2GDS flow (Synthesis, Place & Route and sign off) including Synthesis, Constraints definitions, floor-planning, Placement, CTS, Routing, timing Sign-Off, DFT, IR/EM signoff
Be responsible for RTL2GDS planning, effortestimation and implementation
Be responsible for the quality of the RTL2GDS flow fulfilling the required KPIs
Be a key contributor working together with the design team, the custom layout team and the Digital Physical team members, to reach the timing closure and signoff criteria as planned
Interface with top level, digital and analog design teams both local and from other sites to ensure a smooth integration
Implement, update and improve the scripts used in the RTL2GDS Design flow
Mentor younger engineers
Requirements
As a driven and results-oriented leader, you are motivated by the pursuit of ambitious goals while remaining strongly committed to delivering top-quality product development. You believe in the power of asking questions and challenging assumptions to ensure that we consistently achieve high-quality outcomes. Collaborating with management and peers across different sites, you strive to optimize our processes and drive towards the best results with maximum efficiency.
You are best equipped for this task if you have:
University degree in Electrical Engineering, Computer Science or similar field
At least 6 years of experience in implementing complex SoC designs from RTL to GDS – preferred in an UNIX environment
Expertise in Synthesis, Constraintsdefinitions, floor-planning, power, CTS, STA
Very good knowledge in Place and Route tools, floor planning and IR/EM sign off tools
Skills acquired by previous usage of various CAD tools like: Genus, Innovus, ICC/ICC2, Calibre, StarRC – Primetime and Design Compiler is considered a plus
Very good scripting knowledge using TCL, Python and/or Perl
Very good communication skills and fluency in English
