As a Principal Engineer for Functional Verification, you will be an integral part of a dynamic verification team, leveraging cutting-edge verification tools and methodologies to facilitate the functional verification of large and complex memory devices. Your will act as an expert in verification topics, effectively steering ongoing work, and providing technical mentorship to other team members. You will play a deep and crucial role in testbench development and verification closure, utilizing System Verilog and UVM to ensure the highest standards of quality and efficiency.
Employer Profile
Semiconductors
Responsibilities
In your new role you will:
Design self-checking test benches using modern verification techniques
Design verificationcomponents such as functional and behavioral models, monitors, and checkers
Implement functional coverage and assertions using System Verilog and UVM
Develop test and functionalcoverageplans based on device specifications
Analyze and debug simulation failures, as well as analyzing functional coverage results to guarantee zero defect outcomes
Manage verification teams through all design phases
Requirements
BSc degree in Electrical Engineering, or a related field
At least 10 years of experience in IC verification with constrained-random, coverage driven verification closure
Deep knowledge in IP and SoCverificationconcepts and implementation with UVM methodology
Deep knowledge in verification concepts, methodologies, EDA tools, including all design phases and BIST activities
Experience developing and working with verification languages like: System Verilog, OVM, UVM
A solid understanding of verification concepts and experience in designing class-based test benches
Knowledge and experience in C coding, Power aware, and gate level simulation
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