Job-ID: ID Senior Staff Engineer Functional Verification
Full time
Bucharest
Senior
11-05-2026
As a Senior Staff Engineer for Functional Verification, you will be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices.
Arbeitgeberprofil
Semiconductors
Verantwortlichkeiten
In your new role you will:
Design self-checking test benches using modern verification techniques
Develop verification plans based on device specifications and architecture specifications
Implement and maintain the verification emvironment using System Verilog and UVM methodology
Analyze and debug simulation failures, as well as analyze functional coverage results to guarantee zero defect outcomes
Lead and mentor junior verification engineers, as part of a project
Be part and be responsible for the verification of pre silicon verificationphase
Anforderung
As a driven and results-oriented individual, you excel in environments where ambitious goals and top-quality product development converge. You consistently deliver high-quality results, fulfilling your tasks with dedication and precision. As a team player, you possess a unique ability to think and act cooperatively, establishing successful collaborations with other teams within Infineon. Your cooperative mindset enables you to navigate complex projects with ease, fostering a culture of mutual support and driving collective success.
You are best equipped for this task if you have:
University Degree in Electronics Engineering or similar or equivalent degree
At least 7 years of project experience in IC verification. Experience with constrained-random, coverage driven verification environments is a plus
Experience developing and working with verification languages, such as System Verilog, and verification methodologies such as OVM, UVM
A solid understanding of verification concepts and experience designing class-based test benches
Knowledge and experience in C coding, OOP, Power aware, and gate level simulation
