In your new role, you will:
• Contribute to/coordinate Digital Design activities for different projects (effort estimations and plan, participate to specification, concept and interdisciplinary reviews, define and implement the mass production test blocks).
• Elaborate architecture and testbenches for each allocated module.
• Implement RTL and perform RTL and Gate level simulations.
• Generate and handle Clock, reset and LFO trees and perform parasitic extraction.
• Perform Synthesis, Equivalence check, Static timing analysis and provide area estimations.
• Implement ECO scripts (timing ECO and functional ECO) and also perform ECO from code and cells replacement.
• Have ATPG knowledge, check design for timing violations
• Perform power simulations and analysis is a plus.
• Work in “Analog on top” and “Digital on top” flows, implement mixed signal P&R flow and perform LVS, DRC checks on released GDS, implement timing driven and physical constraints.
You are best equipped for this task if you have:
• A degree in Electrical/Electronic Engineering or equivalent.
• At least 3 years experience in Digital Design engineering positions.
• Proven experience in RTL Implementation using SystemVerilog/VHDL.
• Good understanding of Digital backend flow.
• Knowledge of a scripting language like Python would also be a plus.
• Good command of English Language.