As a Functional Verification Engineer you will work closely with design team to ensure that exhaustive
verification design & verification goals are achieved.
In your new role you will:
• Review functional specifications and define the verification strategy (e.g. verification plan and verification environment architecture) based on the HW specification.
• Build the verification environment following the verification methodologies (i.e. UVM, eRM).
• Implement the verification model of the DUT and the verification components for driving, monitoring and checking different digital modules, at SOC level and mixed signal testing.
• Develop test scenarios and functional coverage based on the verification plan.
• Create and support innovative ideas in your field of knowledge collaboratively and have measurable impact on working results on a local basis and within organizational area.
• Contribute to success and give technical guidance in the project / team.
• Share knowledge within project / team and demonstrate active knowledge transfer and best practice
You demonstrate strong communication skills, know how to establish lasting relationships and networks, clarify areas of responsibility, coordinate your work with colleagues, and regularly share your insights with them. You actively contribute to putting decisions to work as soon as they are taken and push ideas to their full implementation and application by supporting the team to excellence.
You are best equipped for this task if you have:
• Studies in Electrical/Electronic Engineering or equivalent
• Experience with a High Level Verification Language (System Verilog/Specman).
• Good understanding of Verilog/VHDL and the ability to debug digital circuits on RTL and gate level.
• Knowledge of Object Oriented Programming.
• Knowledge of a scripting language (e.g. TCL, bash, perl, Python).
• Good command of English Language.